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Ouroboros Chronos: Permissionless Clock Synchronization via Proof-of-Stake
Blockchain Consensus Clock Synchronization
2019/7/22
Proof-of-stake (PoS) has been shown to be a suitable replacement—in many respects—for the expensive proof-of-work mechanism introduced by the Bitcoin protocol. Nevertheless, one common and seemingly i...
Sliding-Window Correlation Attacks Against Encryption Devices with an Unstable Clock
Power analysis SW-CPA Jittered clocks
2018/4/9
Power analysis side channel attacks rely on aligned traces. As a counter-measure, devices can use a jittered clock to misalign the power traces. In this paper we suggest a way to overcome this counter...
Faulty Clock Detection for Crypto Circuits Against Differential Fault Analysis Attack
AES differential fault analysis side-channel attacks
2016/12/8
Differential fault analysis attack is a kind of serious threat to cryptographic devices.
Previous protection schemes for crypto devices are not designed specifically against this kind of
attacks. At...
System Clock and Power Supply Cross-Checking for Glitch Detection
System Clock Power Supply Cross-Checking
2016/12/8
Cryptographic systems are vulnerable to different kinds of fault injection attacks. System clock glitch is one of the most widely used fault injection methods used in different attacks. In this paper,...
Faulty Clock Detection for Crypto Circuits Against Differential Fault Analysis Attack
Clock glitch detection AES differential fault analysis
2016/1/6
Clock glitch based Differential Fault Analysis (DFA) attack is a serious threat to cryptographic
devices. Previous error detection schemes for cryptographic devices target improving the
circuit reli...
Synchronous Sampling and Clock Recovery of Internal Oscillators for Side Channel Analysis
side-channel analysis acquisition
2014/3/13
Measuring power consumption for side-channel analysis typically uses an oscilloscope, which measures the data relative to an internal sample clock. By synchronizing the sampling clock to the clock of ...
Clock-Controlled Shift Registers for Key-Stream Generation
Clock-Controlled Shift Registers Key-Stream Generation
2009/4/16
In this paper we estimate the period of the sequence generated
by a clock-controlled LFSR with an irreducible feedback polynomial
and an arbitrary structure of the control sequence, as well as some ...